module instMemory (
    input wire clk,
    input wire rst,
    input wire [31:0] pc_in,
    output reg [31:0] pc_out,
    output reg [31:0] now_inst
); 

    //使用数组模拟存储器
    reg [31:0] mem[0:16];

    initial begin
        /**
            addi r4 r4 41
            addi r12 r12 105
            add r3 r4 r12
            addi r5 r5 41
            addi r6 r6 41
            addi r7 r7 41
            addi r8 r4 42
            add r4 r8 r3
            add r11 r8 r12

        **/
        //不准摆烂的情况下，要加上旁路技术
        mem[0] = 32'b00000010100100100000001000010011;
        mem[1] = 32'b00000110100101100000011000010011;
        mem[2] = 32'b00000000010001100000000110110011;
        mem[3] = 32'b00000010100100101000001010010011;
        mem[4] = 32'b00000010100100110000001100010011;
        mem[5] = 32'b00000010100100111000001110010011;
        mem[6] = 32'b00000010101000100000010000010011;
        //加上摆烂指令以后能解决写后读的问题
        // mem[2] = 32'b00000010100100101000001010010011;
        // mem[3] = 32'b00000010100100110000001100010011;
        // mem[4] = 32'b00000010100100111000001110010011;
        // mem[5] = 32'b00000010101000100000010000010011;
        // mem[6] = 32'b00000000010001100000000110110011;
        mem[7] = 32'b00000000001101000000001000110011;
        mem[8] = 32'b00000000110001000000010110110011;
        mem[9] = 0;
        mem[10] = 0;
        mem[11] = 0;
        // mem[0] = 32'b00000000000000010100000110110111;
        // mem[1] = 32'b00000000000000101100001100110111;
        // mem[2] = 32'b00000000000000000000010010110111;
        // mem[3] = 32'b00000000000000010100010100110111;
        // mem[4] = 32'b00000000001001010000011000110111;
        // mem[5] = 32'b00000000000000000000000010110111;
        // mem[6] = 32'b00000000011000011000010010110011;
        // mem[7] = 32'b00000000000000110000000110110011;
        // mem[8] = 32'b00000000000001001000001100110011;
        // mem[9] = 32'b00000000000100001000000010010011;
        // mem[10] = 32'b11111110101000001100000011100011;
        // mem[11] = 32'b00000000100101100010000000100011;
        mem[12] = 0;
        mem[13] = 0;
        mem[14] = 0;
        mem[15] = 0;
    end

    //在时钟上升沿获取到当前PC对应的指令内容
    always @(posedge clk) begin
        now_inst <= mem[pc_in];
    end

    always @(*) begin
        pc_out = pc_in;
    end
endmodule